The present disclosure relates to electronic circuits, and more particularly, to a partial response receiver and related methods.
In digital systems, data is transmitted as a sequence of level-encoded electrical pulses (i.e., bits) through a signaling path. Electrical pulses transmitted on a band-limited signaling path disperse in time as they travel from a transmitter to a receiver. Time-domain dispersion results in a blending of neighboring pulses. This effect is known as dispersion-type inter-symbol interference (ISI). Dispersion-type ISI becomes more pronounced at faster signaling rates, ultimately degrading the signal quality to the point at which distinctions between originally transmitted signal levels may be lost.
A partial response equalizer (PRE) can be used in a receiver to mitigate dispersion-type ISI that results from transmitting data through a signaling path. A PRE compares each bit in an incoming data signal to multiple threshold levels. The threshold levels are selected based on possible digital sequences of one or more previously received bits in the incoming data signal.
FIG. 1 illustrates a prior art double data rate (DDR) partial response equalizer 100 that samples two bits in an incoming data signal during each period of a sampling clock signal. Sampler circuits 101A-101D compare the incoming data signal VIN to thresholds +/−α along parallel sampling paths to generate sampled bits DPE, DNE, DPO, and DNO, respectively. Sampler circuits 101A-101B are driven by clock signal CLK, and sampler circuits 101C-101D are driven by clock signal CLKB. CLK and CLKB are driven out of phase. Each of multiplexers 104A-104B selects one of the sampled bits based on a previously sampled bit, DO and DE, respectively. The sampled bits selected by multiplexers 104A-104B are stored in latches 105A-105B in response to CLKB and CLK as previously sampled bits DE and DO, respectively.
The delay of the longest feedback path in PRE 100 is shown below in equation (1).TC,Q+TMUX,SO+TSU<1(UI)  (1)
In equation (1), TC,Q is the clock-to-Q output delay of each of latches 105A and 105B, TMUX,SO is the select-to-output delay of each of multiplexers 104A and 104B, TSU is the setup delay of each of latches 105A and 105B, and UI is one unit interval (i.e., bit period) in VIN. Sampling VIN along parallel paths in circuit 100 does not reduce the longest feedback path delay. PRE 100 imposes a lower limit on each unit interval as shown in equation (1). The lower limit on each unit interval may make it difficult to employ conventional partial response designs and their associated benefits as clock rates continue to increase. Therefore, it would be desirable to provide a partial response equalizer that performs the feedback selection in less time.